1. Field of the Invention
Embodiments of the invention relate to a liquid crystal display and a frame rate control method thereof.
2. Discussion of the Related Art
As shown in FIG. 1, an active matrix liquid crystal display reproduces an input image on pixels each including a thin film transistor (TFT) as a switching element. The TFT supplies a data voltage Vdata supplied through a data line to a pixel electrode of a liquid crystal cell Clc in response to a gate pulse (or a scan pulse) supplied through a gate line. Each of the pixels of the active matrix liquid crystal display includes red (R), green (G), and blue (B) subpixels for color representation, and each of the red (R), green (G), and blue (B) subpixels includes the liquid crystal cell Clc, the TFT, a storage capacitor Cst, etc. The liquid crystal cell Clc includes the pixel electrode to which the data voltage Vdata is supplied, a common electrode to which a common voltage Vcom is supplied, and a liquid crystal layer formed between the pixel electrode and the common electrode. Liquid crystal molecules of the liquid crystal layer move based on an electric field applied between the pixel electrode and the common electrode and adjust an amount of light passing through a polarizing plate attached to an upper plate of a liquid crystal display panel.
In FIGS. 1 and 2, “Vdata” is a positive and negative data voltage output from a source driver integrated circuit (IC), and “Vgate” is a gate high or low voltage output from a gate driver IC. The gate pulse is generated at the gate high voltage, which is set to be equal to or greater than a threshold voltage of the TFT, and turns on the TFT. “Cst” is a storage capacitor for holding a voltage of the liquid crystal cell Clc, and “Cgs” is a parasitic capacitance between a gate electrode and a source electrode of the TFT. “Vp(+)” is the positive data voltage charged to the liquid crystal cell Clc, and “Vp(−)” is the negative data voltage charged to the liquid crystal cell Clc.
As shown in FIG. 2, the active matrix liquid crystal display periodically inverts a polarity of the data voltage, so as to reduce degradation of liquid crystals and image sticking. A frame inversion method, a column inversion method, a line inversion method, a dot inversion method, etc. are known as a method for driving the active matrix liquid crystal display.
As shown in FIGS. 1 and 2, the positive data voltage is supplied to the liquid crystal cell Clc for a scan time of an n-th frame period Fn (where n is a positive integer), and then the negative data voltage is supplied to the liquid crystal cell Clc for a scan time of an (n+1)-th frame period (Fn+1). For the scan time of the n-th frame period Fn, the liquid crystal cell Clc is charged to the positive data voltage and is held at the positive voltage Vp(+), which is reduced by ΔVp because of the parasitic capacitance Cgs of the TFT. For the scan time of the (n+1)-th frame period (Fn+1), the liquid crystal cell Clc is charged to the negative data voltage and is held at the negative voltage Vp(−), which is reduced by ΔVp because of the parasitic capacitance Cgs of the TFT. Thus, even if the positive data voltage and the negative data voltage, which are set at the same gray level, are supplied to the liquid crystal cell Clc, a luminance of the liquid crystal cell Clc may change depending on the polarity of the data voltage. If one frame period has a short duration or the liquid crystal cell Clc is held at the data voltage of the same polarity for a short period of time, a user may not recognize a luminance difference. On the other hand, if the duration of one frame period increases or a hold time of the liquid crystal cell Clc at the data voltage of the same polarity increases, the user may recognize the luminance difference.
ΔVp changes depending on the parasitic capacitance Cgs of the TFT as indicated by the following Equation (1).
                              Δ          ⁢                                          ⁢          Vp                =                              Cgs                          Clc              +              Cst              +              Cgs                                ×          Δ          ⁢                                          ⁢          Vg                                    (        1        )            
In the above Equation (1), ΔVg is a difference between the gate high voltage and the gate low voltage.
Most of the liquid crystal displays have recently used a frame rate control (FRC) method which reduces the number of bits of data and reduces the number of data transfer lines to thereby compensate for a reduction of image quality. The FRC method increases the number of representable gray levels using a compensation method illustrated in FIGS. 3 and 4 while reducing the number of bits of digital video data input to the source driver IC, thereby compensating for a loss of the image quality.
A principle of the frame rate control is described with reference to FIGS. 3 and 4.
FIG. 3 illustrates an example where a FRC compensation value is distributed in terms of time so as to finely adjust a luminance at a gray level less than 1-gray level. As shown in (a) of FIG. 3, if the FRC compensation value ‘1’ is written to subpixels of a pixel array only during one frame period of four frame periods, a viewer may recognize a gray level of the subpixels at one-quarter gray level (i.e., the luminance of 25%) during the four frame periods. As shown in (b) of FIG. 3, if the FRC compensation value ‘1’ is written to the subpixels of the pixel array only during two frame periods of the four frame periods, the viewer may recognize a gray level of the subpixels at one-half gray level (i.e., the luminance of 50%) during the four frame periods. As shown in (c) of FIG. 3, if the FRC compensation value ‘1’ is written to the subpixels of the pixel array only during three frame periods of the four frame periods, the viewer may recognize a gray level of the subpixels at third-quarter gray level (i.e., the luminance of 75%) during the four frame periods.
FIG. 4 illustrates an example of a dithering method for spatially distributing a FRC compensation value so as to finely adjust a luminance at a gray level less than 1-gray level. The dithering method adjusts the number of subpixels, to which the FRC compensation value is written, in a dither mask of a predetermined size including a plurality of subpixels D1 to D4 and spatially distributes the FRC compensation value, so as to finely adjust the luminance at the gray level less than 1-gray level. As shown in (a) of FIG. 4, when a dither mask including, for example, 2×2 subpixels is used, if the FRC compensation value ‘1’ is written to one subpixel D1 in the dither mask, the viewer may recognize a gray level of the dither mask at one-quarter gray level (i.e., the luminance of 25%). As shown in (b) of FIG. 4, if the FRC compensation value ‘1’ is written to two subpixels D2 and D3 in the dither mask, the viewer may recognize a gray level of the dither mask at one-half gray level (i.e., the luminance of 50%). As shown in (c) of FIG. 4, if the FRC compensation value ‘1’ is written to three subpixels D2, D3, and D4 in the dither mask, the viewer may recognize a gray level of the dither mask at three-quarter gray level (i.e., the luminance of 75%).
The FRC applied to the liquid crystal display generally uses both the time distribution method of FIG. 3 and the spatial distribution method of FIG. 4 to implement a method illustrated in FIG. 5. The FRC compensation value may be successively written to the same subpixels. In this instance, a luminance of the subpixels, to which the FRC compensation value is successively written, is greater than a luminance of other subpixels. Therefore, luminance uniformity of the liquid crystal display and color representation characteristic are reduced. For example, a specific color may be more remarkably represented than other colors. To solve the above problem, the FRC previously sets FRC patterns defining a position of the subpixels, to which the FRC compensation value will be written, to various forms, circulates the FRC patterns in each frame period, and changes the position of the subpixels, to which the FRC compensation value is written, in each frame period. For example, as shown in FIG. 5, a position of the subpixels, to which the FRC compensation value is written, in FRC patterns P1 and P3 used in odd-numbered frame periods N and N+2 alternates with a position of the subpixels, to which the FRC compensation value is written, in FRC patterns P2 and P4 used in even-numbered frame periods N+1 and N+3.
As described above, the polarity of the data voltage supplied to the pixel array of the liquid crystal display is inverted in terms of time and space based on a polarity inversion method. As shown in FIG. 5, the FRC compensation value may be written to subpixels, which are driven at the same polarity for a long period of time, in the pixel array driven based on the polarity inversion method. In this instance, the polarities of the subpixels, to which the FRC compensation value is written, are dominant to one polarity. For example, in FIG. 5, the FRC compensation value is written to subpixels charged to the positive data voltage. Thus, because the FRC compensation value is successively written to subpixels charged to the data voltage of the same polarity for a long period of time, the image sticking may appear due to the DC drive of the subpixels.